Silicon-based complementary metal-oxide-semiconductor (CMOS) electronics have undergone remarkable progresses over the past 40-50 years. It is expected that, with new materials and device structures continuously being introduced for boosting the performance and reducing the cost, the CMOS electronics will continue to be the workhorse of the information technologies.
However, the silicon-based electronics are facing increasing amount of challenges in both low-end and high-end market segments.
In the low cost segment of the market, organic electronics have made tremendous progress over the last decade. A combination of a special type of organic materials and low-cost, large area fabrication processes (such as printing) enables the production of thin, lightweight, flexible and low-cost electronic devices. Currently, performance of the organic electronic devices is limited by very low mobility of charge carriers in the organic materials. This means the fabrication of radio frequency (RF) circuitries or fast display devices remains a challenge. Once these problems are solved, the organic electronic devices will be competing with the silicon-based devices.
In the high-end market segment, the CMOS microelectronics technologies are rapidly approaching the theoretical scaling limits. Further scaling efforts are expected to expend the devices into nano-electronics territory. For instance, a variety of devices based on the integration of individual high aspect ratio nanoparticles, which have a diameter of a few nanometers and a length of about 0.1-10 micron, have been demonstrated. A typical example of the high aspect ratio nanoparticles is carbon nanotubes (CNTs). Examples of such devices include field effect transistors (FETs), diodes, logic circuit elements, optical emission devices and different types of sensors.
In particular, one type of the carbon nanotubes, semiconducting single wall carbon nanotubes (SWNTs), is very promising as one-dimensional electronic material. SWNTs have some exceptionally interesting properties, for example a room temperature charge mobility as high as 100,000 cm2/Vs (which is more than an order of magnitude larger than the mobility of crystalline silicon), current carrying capacity up to 109 A/cm2 and ON/OFF current ratio larger than 105. These unique properties of the SWNTs have prompted researchers to fabricate devices with better performance and higher scaling density than traditional silicon-based electronic devices.
To the date, industrial scale processes for mass fabrication of single CNT based electronic circuits are not well established. Besides, because of the limited current-carrying capacity of individual CNT, multiple CNTs aligned side by side in a single device would be required in order to match the current density of a counterpart silicon-based device. A precise positioning of individual CNTs is beyond the capability of current growth and assembly technologies and it presents a major technological hurdle for CNT-based electronic applications.
On the other hand, instead of trying to manipulate individual high aspect ratio nanoparticles in the device fabrication, using a naturally formed layer of high aspect ratio nanoparticles in the device structure has been contemplated. A typical example is a carbon nanotube network (CNTN), which is an array of CNTs deposited on a substrate, much like a porous thin film. Using processes known in the art, randomly oriented CNTNs can be produced straightforwardly. If the density of the CNTN is sufficiently high, the nanotubes will interconnect and form continuous electrical paths. An attractive feature of the CNTN is that it retains many of the interesting electronics properties of an individual CNT while providing the processing capabilities for mass fabrication. Compared to organic or polymer semiconductive materials, CNTNs offer 10 times higher charge mobility, lower operating voltages and ability to be placed onto a wide variety of substrates.
The methods for fabricating the CNTNs may include: (1) localized synthesis processes in which a CNTN substrate is also a CNT growth substrate, and (2) remote synthesis processes in which CNTs are produced separately from the substrate, and are deposited on the substrate later on.
In the localized CNTN synthesis, a CNTN is grown on the substrate from nanometer-sized catalyst particles deposited at certain locations on the substrate. In this process, the CNT growth normally requires high growth temperatures (typically above 700° C.). This means that the substrate must be able to withstand elevated temperatures. The localized synthesis may be unacceptable for many substrates used in low cost electronics, especially for various types of polymer substrates.
The remote synthesis process allows for the CNTNs being produced on low temperature substrates such as silicon, glass and various polymers. The growth of the CNTs and the deposition of the CNTNs are separated in time and space. For example, CNTs can be grown in a free form and then be dispersed in a solution. The solution can be deposited on a substrate via spin coating or spraying. Then, the substrate is dried. It should be pointed out that dispersion of CNTs in a solution is an extremely difficult process.
Recently, an aerosol based remote synthesis process has been proposed. In the process, CNTs are synthesized in gas and then dry deposited on the substrate directly from the gas phase. A homogeneous CNTN is formed on the substrate at a low temperature. Compared to the solution-based methods, the aerosol-based method includes fewer steps. Therefore it is simple, low-cost and acceptable for mass production.
After a CNTN is deposited on the substrate, the microelectronic device structures are built on the substrate. Traditional integrated circuit (IC) fabrication methods may be used for patterning the CNTN layer, and depositing and pattering dielectric and metal layers. The simplest and most widely used way of patterning the CNTN in micrometer scale is the standard lithography and lift-off process.
For further improving device performance and manufacturing yield, it would be highly desirable if the nanotubes in the CNTN were at least partially oriented in a certain direction. This way, the subsequent device fabrication can advantageously use the direction of the orientation for enhancing the current carrying capability of the interconnecting nanotubes. There are known methods for CNT deposition and even CNT alignment. However, these methods are complex and expensive. In this disclosure, a low cost process for making a structure of high aspect ratio nanoparticles is introduced. The process is based on low temperature aerosol chemical vapor deposition and it is suitable for mass-production. In particular, the process is suitable for making CNTN substrates for CNT based nanoelectronic device fabrication. What's more, the process allows for the high aspect ratio nanoparticles being at least partially aligned. Further, a device fabrication method advantageously using the orientation of the nanoparticles for enhancing the current carrying capability is also introduced.